This invention relates to a semiconductor integrated circuit that comprises a plurality of interconnection layers and to a method of designing such a semiconductor integrated circuit. The present invention pertains in particular to achieving a reduction of the area occupied by interconnection lines in order to increase the level of integration of the semiconductor integrated circuit.
With the rapid improvement in the level of semiconductor integrated circuit integration, reduction in interconnection line area and increase in high electric current density are problems the semiconductor industry will have to face in the near future. In recent years, various approaches, for example, to interconnection line materials with high electromigration (hereinafter referred to as xe2x80x9cEMxe2x80x9d) resistance, new semiconductor device structures, and layout design techniques allowing for the EM resistance have been proposed, have been made.
As an interconnection line material, a copper- or titanium-added aluminum alloy is currently used for semiconductor integrated circuits. A structure (called the xe2x80x9cplug structurexe2x80x9d) is adopted, more specifically tungsten (W) is filled into a contact hole or into a via hole by means of an LPCVD (low-pressure chemical vapor deposition) process for establishing electrical continuity between interconnection lines of vertically disposed interconnection layers constructed of an aluminum alloy.
Various layout design techniques have been proposed. Japanese patent applications, which have been laid open under publication nos. 3-289155 and 4-107953, respectively, each disclose a layout design technique in which the waveforms and values of electric currents which flow in individual interconnection lines are extracted by arithmetic operations for reflection on the layout.
The fact that the EM depends upon the current density, upon the interconnection line width, and upon the current waveform has been known to exist (see xe2x80x9cThe Enhancement of Electromigration Lifetime under High Frequency Pulsed Conditions,xe2x80x9d IEICE Trans. Fundamentals, Vol. E77-A, No. 1, p.195, 1994 by K. Hiraoka and others). Additionally, faulty mode, in which voids are produced due to electromigration in an aluminum alloy overlying a plug structure of tungsten, has lately attracted considerable attention (see xe2x80x9cThe Effect of Copper Concentration on the Electromigration Lifetime of Layered Aluminum-Copper (Ti-AlCu-Ti) Metallurgy with Tungsten Diffusion Barriers,xe2x80x9d Proc. of IEEE, VMIC, p.359, 1992 by R. G. Filippi and others). Further, it has been proved that EM in an aluminum alloy overlying a tungsten-plug depends upon the interconnection line length (see. xe2x80x9cPermitted Electromigration of Tungsten-plug Vias in Chain for Test Structure with Short Inter-plug Distance,xe2x80x9d Proc. of IEEE, VMIC, p.266, 1994 by T. Aoki and others). Furthermore, the fact that the EM depends upon the overlap margin (reservoir length) of aluminum interconnection line and tungsten-plug has been known to exist (see xe2x80x9cAn Electromigration Failure Model of Tungsten Plug Contacts/Vias for Realistic Lifetime Prediction, xe2x80x9dVLSI Symp. p.192, 1996 by H. Kawasaki and C. K. Hu).
Table 1 above is a list showing the foregoing parameters having affection on the electromigration, and the tendency of such affection.
Integrating the foregoing prior art techniques, it is conceptually possible to incorporate the dependence of the electromigration upon the parameters shown in Table 1 into the foregoing Japanese patent applications. However, incorporation of a single EM dependence parameter into such a technique requires a process of verifying millions of interconnection lines. Further, providing corresponding tables to the parameters and verifying interconnection lines is enormously time-consuming and is impractical at all. Accordingly, these techniques have not been put into practical use yet.
Practically, design rules allowing for conditions when the worst happens are applied to all interconnection lines. For example, in Japanese patent application pub. no. 4-107953 which utilizes current values, an estimation of the maximum permissible current density at a point under worst condition is formed. For example, if the maximum permissible electric current of an interconnection line having a width of 1 micrometer is determined at 1 milliampere, then it is determined such that an interconnection line having a width of 2 micrometers is formed at a point at which an electric current of 2 milliampere flows. Since maximum permissible current density needed at a point under the worst condition is applied to all locations, safety factor more than necessary is incorporated. As a result, although the miniaturization of individual semiconductor elements advances, it is difficult to achieve a reduction of the interconnection line dimensions therefore producing a bar to improving the level of semiconductor integrated circuit integration.
Accordingly, it is a first object of the present invention to provide a high-density semiconductor integrated circuit and a method for designing such a semiconductor integrated circuit to the miniaturization of semiconductor elements. More specifically, based on the knowledge that the affects of the interconnection on EM vary depending upon the working conditions of individual interconnection lines even at an identical amount of electric current. Parameters, which have important affects on EM, are selected from interconnection working conditions. The interconnection line form is determined in relation to these parameters. Within a range which does not affect the EM resistance, the dimensions of interconnection lines are reduced as small as possible.
In order to achieve the first object, the present invention provides semiconductor integrated circuits and a recording medium.
Overlap margins, needed for interconnection lines, are also a bar to achieving a reduction of the interconnection line dimensions and a bar to providing high-density semiconductor integrated circuits.
It is a second object of the present invention to provide a high-density semiconductor integrated circuit and a method for designing such a semiconductor integrated circuit to the miniaturization of semiconductor elements. More specifically, based on the knowledge that even if the plug position and the interconnection line position slightly differ from each other, this will not affect EM when an electric current flowing the plug is very small. The overlap margin is reduced according to the electric current flowing in plugs.
In order to achieve the second object, the present invention provides semiconductor integrated circuits and a recording medium.
The present invention provides a design method for a semiconductor integrated circuit having components formed in a semiconductor substrate, a plurality of interlayer dielectric films and a plurality of interconnection layers alternately formed over said semiconductor substrate, and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film wherein said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component, said semiconductor integrated circuit design method comprising:
(a) a first step including:
selecting, as a parameter which affects electromigration resistance at the interface between an interconnection line and a plugging member, a specific parameter including at least one of an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line capacity, an interconnection line thickness, and an overlap margin;
dividing, according to a working condition relative to said specific parameter, the permissive current amount of a plugging member into a plurality of zones; and
performing the setting of a representative value common in each of said zones; and
(b) a second step including:
determining the representative value of one of said zones to the value of said specific parameter as the permissible current amount of said plugging member; and
determining the total opening area of each said connecting window and the plane form of each said interconnection line according to said permissible current amount.
A permissive current amount, allowing for the dependence of EM on various types of parameters, is found. According to the permissive current amount, the total opening area of a connecting window including one or more connecting holes is divided into a plurality of zones. Such arrangement makes it possible to easily achieve a reduction of the area occupied by interconnections within the range that does not affect EM resistance, without having to prepare complicated tables or without having to perform huge amounts of arithmetic processing. As a result, higher-density semiconductor integrated circuits can be fabricated.
It is preferred that in said second step said semiconductor integrated circuit is subjected to schematic placement/interconnection before the determination of said permissible current amount, the total opening area of each said connecting window is determined according to a permissible current amount determined based on the result of said placement/interconnection, and the form of each said interconnection line is corrected according to said total opening area of each said connecting window.
As a result of such arrangement, the correct value of a specific parameter can be determined from a layout obtained by a schematic placement/interconnection process. This enables the design of a layout with the exact total opening area of a connecting window including at least one connecting hole and the fine form of interconnection.
It is preferred that the semiconductor integrated circuit design method further comprises, at least before said second step, a step of subjecting said semiconductor integrated circuit to placement/interconnection wherein in said second step when the total opening area of each said connecting window determined according to the result of said placement/interconnection disagrees with said working condition said placement/interconnection performed is corrected.
The degree of allowance is set small in advance and placement and interconnection is carried out. This makes it possible to check whether the total opening area of a connecting window including at least one connecting hole determined by the placement/interconnection agrees with the working condition, to correct the placement/interconnection.
It is preferred that the approximate capacity of each said interconnection line is predetermined and that in said first step an approximate interconnection line capacity is included in said specific parameter and the representative value of a zone having an approximate interconnection line capacity below a given capacity is set in such a way as to exceed the representative value of a zone having an approximate interconnection line capacity above said given capacity.
It is preferred that the length of each said interconnection line is predetermined and that in said first step an interconnection line length is included in said specific parameter and the representative value of a zone having an interconnection line length below a given value is set in such a way as to exceed the representative value of a zone having an interconnection line length above said given value.
When the interconnection line capacity is great, the metallic atoms from the interface of a plugging member and an interconnection line can diffuse easily. This accelerates electromigration. On the other hand, when the interconnection line length is short, the resistance against the movement of metallic atoms is enhanced. As a result, the phenomenon of electromigration becomes unlikely to occur. Taking into account these facts, the total opening area of a connecting window including one or more connecting holes which are brought in connection with an interconnection line whose approximate capacity is small or whose length is short, is reduced. It accordingly becomes possible to reduce the dimensions of interconnection lines according to the reduction of the total window opening area. Generally speaking, as elements are reduced in size, the interconnection line length is likewise reduced. The enables the provision of higher-density semiconductor integrated circuits to semiconductor integrated circuit miniaturization.
It is preferred that the approximate width of each said interconnection line is predetermined and that in said first step an approximate interconnection line width is included in said specific parameter and the representative value of a zone having an approximate interconnection line width below a given value is set in such a way as to exceed the representative value of a zone having an approximate interconnection line width above said given value.
When the approximate width of an interconnection line is decreased, this results in a so-called xe2x80x9cbamboo structurexe2x80x9d in which the grain boundaries of a metal constructing the interconnection line exist only in the interconnection line width direction or results in a structure similar to the bamboo structure. Since there exist no grain boundaries in the interconnection line direction (even if there exist grain boundaries the degree of the existence is negligible), the phenomenon of electromigration is unlikely to occur. In accordance with this design method, the total opening area of a connecting window having one or more connecting holes which are brought in connection with interconnection lines having such a structure can be reduced. Correspondingly to this, it becomes possible to achieve a reduction of the area occupied by interconnection. Generally speaking, as elements are reduced in size, the interconnection line width is likewise reduced. The enables the provision of higher-density semiconductor integrated circuits to semiconductor integrated circuit miniaturization.
It is preferred that the length and the approximate width of each said interconnection line are predetermined and that in said first step both an interconnection line length and an approximate interconnection line width are included in said specific parameter and the representative value of a zone having an interconnection line length and an approximate interconnection line width, at least one of which falling below a corresponding one of given values, is set in such a way as to exceed the representative value of a zone having an interconnection line length and an approximate interconnection line width, both of which exceeding said given values.
It is preferred that it is predetermined whether the waveform of an electric current that flows in a plugging member is a unidirectional current or a bidirectional current and that in said first step an electric current waveform is included in said specific parameter and the representative value of a zone in which a bidirectional electric current flows is set in such a way as to exceed the representative value of a zone in which a unidirectional electric current flows.
In a bi-directional electric current which flows in each direction, the direction in which atoms move alternately changes, whereby the metallic atoms near the interface of a plugging member and an interconnection line make little movement. Taking this into account, the total opening area of a connecting window having at least one connecting hole through which a bi-directional electric current flows can be reduced. Accordingly, a reduction of the interconnection line area can be achieved.
It is preferred that it is determined whether a unidirectional current waveform is a pulse current or a continuous current and that in said first step a unidirectional current waveform is included in said specific parameter and the permissible current of a zone in which said unidirectional current is a pulse current is set in such a way as to exceed the permissible current of a zone in which said unidirectional current is a continuous current.
If the electric current value is the same, the number of electrons that move is greater in electric current which flows in only one way in pulse-like manner in comparison with a continuous electric current and the movement of metallic atoms is unlikely to occur. Taking this into account, the total opening area of a connecting window having at least one connecting hole can be reduced. Accordingly, a reduction of the interconnection line area can be achieved.
It is preferred that the direction of an electric current which flows between a plugging member and an interconnection line is predetermined and that in said first step an electric current flow direction is included in said specific parameter and the permissible current of a zone in which an electric current flows from a plugging member to an interconnection line is set in such a way as to exceed the permissible current of a zone in which an electric current flows in the opposite direction.
Where the electric current flow direction is from plugging member to interconnection line, the electrons move in the opposite direction (from line to plug), there is made little movement of the near-interface metallic atoms. Taking this into account, the total opening area of a connecting window having at least one connecting hole can be reduced. Accordingly, a reduction of the interconnection line area can be achieved.
It is preferred that it is predetermined that pMISFETs and nMISFETs are mounted, as said components, in said semiconductor substrate and that said current flow direction is decided by whether said component is a pMISFET or an nMISFET.
It is preferred that the basic dimensions of said connecting holes are unified and that in said step of determining the total opening area of each said connecting window the number of connecting holes is determined.
Accordingly, this design method simplifies the processing of design of connecting holes.
The present invention provides a design method for a semiconductor integrated circuit having components formed in a semiconductor substrate, a plurality of interlayer dielectric films and a plurality of interconnection layers alternately formed over said semiconductor substrate, and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film wherein said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component, said semiconductor integrated circuit design method comprising:
(a) a first step including:
selecting, as a parameter which affects electromigration resistance at the interface between an interconnection line and a plugging member, a specific parameter including at least one of an electric current amount, an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line thickness, and an interconnection line capacity;
dividing, according to a working condition relative to said specific parameter, the overlap margin between an interconnection line and a connecting window into a plurality of zones; and
performing the setting of a representative value common in each of said zones; and
(b) a second step including:
determining the representative value of one of said zones to the value of said specific parameter as the overlap margin between each said interconnection line and each said connecting hole.
This design method makes it possible to provide a reduction of the overlap margin (the reservoir length) of connecting windows and interconnection lines within the range that does not affect electromigration. Accordingly, a reduction of the interconnection line area can be achieved.
It is preferred that determination of an overlap margin in said second step is carried out after subjecting said semiconductor integrated circuit to schematic placement/interconnection and finding the value of said specific parameter from the result of said schematic placement/interconnection and that said semiconductor integrated circuit design method further comprises, after said overlap margin determination, a step of correcting said schematic placement/interconnection according to said overlap margin.
In accordance with this design method, the exact value of a specific parameter is determined from a layout produced by schematic placement and interconnection for correct determination of an overlap margin at strict allowance. This enables the design of a layout in which the interconnection line form is appropriate and fine.
It is preferred that the semiconductor integrated circuit design method further comprises, at least before said second step, a step of subjecting said semiconductor integrated circuit to placement/interconnection and that in said second step when the overlap margin between an interconnection line and a connecting window determined according to the result of said placement/interconnection disagrees with said working condition said placement/interconnection performed is corrected.
The degree of allowance is set small in advance and placement and interconnection is carried out. This makes it possible to check whether the total opening area of a connecting window including at least one connecting hole determined by the placement/interconnection agrees with the working condition, to correct the placement/interconnection.
It is preferred that the length of each said interconnection line is predetermined and that in said first step an interconnection line length is included in said specific parameter and the representative value of a zone having an interconnection line length below a given value is set in such a way as to fall below the representative value of a zone having an interconnection line length above said given value.
It is preferred that the approximate width of each said interconnection line is predetermined and that in said first step an approximate interconnection line width is included in said specific parameter and the representative value of a zone having an approximate interconnection line width below a given value is set in such a way as to fall below the representative value of a zone having an approximate interconnection line width above said given value.
It is preferred that in said first step the current density of an electric current flowing in a plugging member is included in said specific parameter and that the representative value of a zone is set to decrease as the current density of a plugging member of said zone increases.
It is preferred that in said first step said common representative values are set such that a zone in which an electric current flowing between an interconnection line and a plugging member is a continuous and unidirectional current, a zone in which said electric current is a unidirectional and pulse-like current, and a zone in which said electric current is a bidirectional current are assigned respective representative values which are set to increase in that order.
It is preferred that it is determined whether the waveform of said unidirectional current is a pulse current or a continuous current and that in said first step a unidirectional current waveform is included in said specific parameter and the representative value of a zone in which said unidirectional current is a pulse current is set in such a way as to fall below the representative value of a zone in which said unidirectional current is a continuous current.
It is preferred that the direction of an electric current which flows between a plugging member and an interconnection line is predetermined and that in said first step an electric current direction is included in said specific parameter and the representative value of a zone in which an electric current flows from a plugging member to an interconnection line is set in such a way as to fall below the representative value of a zone in which an electric current flows in the opposite direction.
Accordingly, a further reduction of the overlap margin is possible to achieve under working conditions which do not affect electromigration with respect to each of the foregoing parameters.
The present invention provides a semiconductor integrated circuit comprising:
components formed in a semiconductor substrate;
a plurality of interlayer dielectric films and a plurality of interconnection layers, said interlayer dielectric films and said interconnection layers being formed in alternating manner over said semiconductor substrate; and
plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film;
wherein:
said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component; and
the total opening area of each said connecting window and the plane form of each said interconnection line are set such that each of zones, which result from division according to a specific parameter including at least one of an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line capacity, an interconnection line thickness, and an overlap margin at an interconnection line-plugging member interface, has a common total connecting window opening area and a common interconnection line plane.
Within the range that does not affect the electromigration resistance, the formation of connecting windows and interconnection lines are performed in order that the total connecting window opening area may belong in a small zone, and the interconnection line area can be reduced. Additionally, as described above, design, capable of realizing such a structure, is easy to perform. The cost of fabricating semiconductor integrated circuits is held within a practically permissive range.
With respect to the semiconductor integrated circuit of the present invention, corresponding manners to cases in which the specific parameter includes, for example, the electric current density, may be employed.
The present invention provides a semiconductor integrated circuit comprising:
components formed in a semiconductor substrate;
a plurality of interlayer dielectric films and a plurality of interconnection layers, said interlayer dielectric films and said interconnection layers being formed in alternating manner over said semiconductor substrate; and
plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film;
wherein:
said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component; and
the overlap margin between each said interconnection line and each said connecting window is set such that each of zones, which result from division according to a specific parameter including at least one of an electric current density, an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line thickness, and an interconnection line capacity at an interconnection line-plugging member interface, has a common interconnection line-connecting window overlap margin.
Within the range that does not affect the electromigration resistance, a layout is designed in order that the connecting window overlap margin may belong in a small zone, and the interconnection line area can be reduced. Additionally, as described above, design, capable of realizing such a structure, is easy to perform. The cost of fabricating semiconductor integrated circuits is held within a practically permissive range.
With respect to the semiconductor integrated circuit of the present invention, corresponding manners to cases in which the specific parameter includes, for example, the electric current density, may be employed.
The present invention provides a computer-readable recording medium for storing a design procedure for a semiconductor integrated circuit having components formed in a semiconductor substrate, a plurality of interlayer dielectric films and a plurality of interconnection layers alternately formed over said semiconductor substrate, and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film wherein said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component, said recording medium storing a program for the execution of a first procedure and a second procedure,
wherein:
(a) said first procedure includes:
selecting, as a parameter which affects electromigration resistance at the interface between an interconnection line and a plugging member, a specific parameter including at least one of an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line capacity, an interconnection line thickness, and an overlap margin, exclusive of an electric current amount;
dividing, according to a working condition relative to said specific parameter, the permissive current amount of said connecting window into a plurality of zones; and
performing the setting of a representative value common in each of said zones; and
(b) said second procedure includes:
determining the representative value of one of said zones to the value of said specific parameter as the permissible current amount of said plugging member.
It is preferred that the computer-readable recording medium further stores a program for the execution of a procedure of subjecting said semiconductor integrated circuit to placement/interconnection before said second procedure and determining, based on the result of said placement/interconnection, the total opening area of each of connecting windows including at least one connecting hole and the form of each said interconnection line, and for the execution of a procedure of determining the total opening area of each said connecting window according to said determined permissible current amount and correcting the form of each said interconnection line according to said total connecting window opening area.
It is preferred that the computer-readable recording medium further stores a program for the execution of a procedure of checking whether the total opening area of each said connecting window determined by said placement/interconnection agrees with said working condition after said second procedure.
The present invention provides a computer-readable recording medium for storing a design procedure for a semiconductor integrated circuit having components formed in a semiconductor substrate, a plurality of interlayer dielectric films and a plurality of interconnection layers alternately formed over said semiconductor substrate, and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film wherein said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component, said computer-readable recording medium storing a program for the execution of a first procedure and a second procedure,
wherein:
(a) said first procedure includes:
selecting, as a parameter which affects electromigration resistance at the interface between an interconnection line and a plugging member, a specific parameter including at least one of an electric current amount, an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line thickness, and an interconnection line capacity, exclusive of an overlap margin;
dividing, according to a working condition relative to said specific parameter, the permissible overlap margin between an interconnection line and a connecting window into a plurality of zones; and
performing the setting of a representative value common in each of said zones; and
(b) said second procedure includes:
determining the representative value of one of said zones determined according to the value of said specific parameter as the overlap margin between said interconnection line and said connecting window.
It is preferred that determination of an overlap margin in said second procedure is carried out, after said semiconductor integrated circuit is subjected to placement/interconnection, according to the result of said placement/interconnection and that said computer-readable recording medium further stores a program for the execution of a procedure of correcting the form of each said interconnection line according to said determined overlap margin.
It is preferred that the computer-readable recording medium further stores a program for the execution of a procedure of checking whether the overlap margin between an interconnection line and a connecting window agrees with said working condition after said overlap margin determination.
The present Invention provides the foregoing recording mediums suitably used in performing process steps of the fabrication of miniaturized semiconductor devices with the aid of computer.